Field of the Invention
The present invention relates to a configuration for crosstalk attenuation in substantially mutually parallel word lines of DRAM circuits, including a decoder provided at a first end of the word line, and a holding transistor.
In mutually parallel word lines of integrated DRAM circuits, crosstalk occurs between adjacent word lines. The crosstalk has an interfering effect which is all the more pronounced the closer the word lines are to one another and the longer the word lines are. The crosstalk is attributable to capacitive coupling between the word lines, which behave like long RC lines.
In order to prevent such crosstalk, a concept previously thought of entails restricting the length of the word lines being used in such a way that voltages generated by crosstalk do not exceed a critical value.
However, restricting the length of the word lines that are used is at odds which the aim of providing DRAM circuits with as many memory cells as possible.